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d a t a sh eet product speci?cation supersedes data of october 1992 file under integrated circuits, ic03 1996 dec 20 integrated circuits PCD4440T analog voice scrambler/descrambler
1996 dec 20 2 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T contents 1 features 2 applications 3 general description 6 pinning information 6.1 pinning 6.2 pin description 7.1 scrambling 7.2 power supply (v dd , v ss ) 7.3 oscillator (osci) 7.4 splitting frequency and mode selection 7.5 serial clock input (scl), serial data input (sda) 7.6 address input (a0) 7.7 i 2 c-bus data configuration 7.8 signal input (in), signal output (out) 8i 2 c bus interface 8.1 bit transfer 8.2 start and stop conditions 8.3 system configuration 8.4 acknowledge 8.5 timing specifications 9 applications 10 handling 11 limiting values 12 characteristics 14.1 introduction 14.2 reflow soldering 14.3 wave soldering 14.4 repairing soldered joints 15 definitions+ 16 life support applications 17 purchase of philips i 2 c components
1996 dec 20 3 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 1 features scrambler or descrambler function scrambling in frequency domain selectable split frequency (up to 10 selections per second) telephony-band filtering included no increase in bandwidth no external components required small signal delay insensitive to distortion and group delay of transmission channel control via serial i 2 c-bus low transfer loss of speech mute option transparent mode high signal input impedance low signal output impedance low power consumption. 2 applications cordless telephones security telephones portable phones private mobile radio (pmr). 3 general description the PCD4440T is a silicon gate cmos integrated circuit intended to be used in cordless telephony, radio, and line telecommunications products utilizing a microcontroller for the control functions. the purpose of the device is to prevent unauthorized listening-in on conversations. a major application is protection of the vulnerable radio link between a ct0 type cordless handset and its base unit. analog scrambling/descrambling is based on the split frequency method realized in a sophisticated switched-capacitor technology. the PCD4440T is compatible with most microcontrollers and communicates via a two line bidirectional i 2 c-bus. 4 ordering information type number package name description version PCD4440T so8 plastic small outline package; 8 leads; body width 7.5 mm sot176-1
1996 dec 20 4 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 5 block diagram fig.1 block diagram. handbook, full pagewidth mgg729 lpf in out bias gen lpf lpf PCD4440T lpf 5 lpf control logic i 2 c-bus interface transparent clocks mute lpf scl osci v dd v ss sda a0 4 128 76 3
1996 dec 20 5 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 6 pinning information 6.1 pinning 6.2 pin description 7 functional description to provide privacy for the end user of a cordless telephone set, the radio-link audio signal must be scrambled. in the microphone of the handset and the incoming telephone line audio path of the base unit a scrambler circuit has to be implemented. consequently the audio signal to the telephone line and to the earpiece must be descrambled. both functions can be fulfilled by the PCD4440T by simply inserting it in the audio path. symbol pin type description scl 1 i serial clock line (i 2 c-bus) sda 2 i serial data line (i 2 c-bus) v ss 3 p negative supply in 4 i signal input out 5 o signal output v dd 6 p positive supply osci 7 i oscillator input a0 8 i slave address input (i 2 c-bus) handbook, halfpage 1 2 3 4 8 7 6 5 mgg728 PCD4440T a0 osci sda v dd out in v ss scl fig.2 pin configuration. 7.1 scrambling the PCD4440Taccomplishes this task by first filtering the incoming signal, limiting the bandwidth to 3500 hz. then the signal is split into a high ( > f s ) and a low ( < f s ) frequency band. both frequency bands are inverted and added again to provide a single output signal. values for 9 split frequencies f s can be controlled by a scramble code table in the microcontroller. control of these split frequencies is accomplished via the serial two-wire i 2 c-bus. in addition to the split frequencies (f s ), a transparent mode and mute instruction can be selected (see table 1). figure 3 shows the signal path for both bands. the lower band path (on the left side of the diagram) operates on frequencies f f s (split frequency), the upper band path (on the right side) on frequencies f 3 f s . the input signal contains frequencies from f 1 up to f 2 . in scrambling mode, the output signal is band limited from f l (300 hz) to f h (3500 hz). in the left path, the input signal is first limited to f s . the following modulator inverts the lower band. f l is folded up to f s , f s down to f l . in general, an input frequency f in is folded to f out =f s +f l - f in . finally the folded signal is band limited to f s again. in the right path, the input signal is first limited to f h . the following modulator inverts the upper band. f s is folded up to f h , f h down to f s . in general, an input frequency f in is folded to f out =f s +f h - f in . finally, the folded signal is band limited to f h again. in the last step, the bands are added and buffered. because of the symmetry of the scrambling process, descrambling is achieved by passing the signal through another PCD4440T. in the transparent mode, the input signal is band limited to 3500 hz. frequencies from 0 to 300 hz are not filtered out.
1996 dec 20 6 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T fig.3 scrambler signal path. handbook, full pagewidth mgg730 lpf 1a lpf 2a lpf 1b lpf 2b ab cd e f 0 a a a a a a a a f 1 f s f h f 2 f f l 0f f s f 1 f l 0f f s f 1 f l 0f f s f 1 f l 0f f h f 2 f s f 1 f l 0f f h f 2 f s f 1 f l 0f f h f 1 f s f 2 f l 0f f h f 2 f 1 f m1 = f l + f s f m2 = f h + f s f s f l ab c ab cd e a b c ab c aa bb cc dd ee b c d e b cd e
1996 dec 20 7 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 7.2 power supply (v dd , v ss ) the positive supply of the circuit (v dd ) must meet the voltage requirement as indicated in the characteristics. to avoid undefined states of the device at power-on, an internal reset circuit clears the logic. the power-on reset has the highest priority; it blocks and resets the complete circuit. 7.3 oscillator (osci) the time base for the PCD4440T is a 3.58 mhz input signal which can be derived from the oscillator output (osco) of philips microcontroller families pcd33xxa or pcf84cxxxa. figure 4 shows the osci connection. 7.4 splitting frequency and mode selection table 1 shows the input codes required to select the various splitting frequencies, and the mute, transparent and scramble/descramble modes. the codes form part of the serial i 2 c-bus message input on the sda line from the microcontroller. table 1 input data codes for splitting frequency and mode selection; note 1 notes 1. input codes other than shown in the table are not allowed. 2. oscillator frequency = 3.58 mhz. d3 d2 d1 d0 hex application f s (2) (hz) 000101 mute mode - 001002 select f s 2641 001103 select f s 1853 010004 select f s 1507 010105 select f s 1279 011006 select f s 1117 011107 select f s 1018 100008 select f s 899 100109 select f s 837 10100a select f s 767 10110bt ransparent mode - 11110f start scramble/descramble mode - handbook, full pagewidth mgg731 27 pf PCD4440T pcd33xxa pcf84cxxxa microcontroller osci 3.58 mhz osco fig.4 osci (oscillator input) connection.
1996 dec 20 8 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 7.5 serial clock input (scl), serial data input (sda) scl and sda are serial clock and data lines which conform to the i 2 c-bus specification. both inputs must be pulled up externally to v dd through resistors of approximately 10 k w . 7.6 address input (a0) a0 is the slave address input and is used to set one bit of the slave address, so as to identify one of two PCD4440T devices connected to the same i 2 c-bus. whether another PCD4440T is connected to the bus or not, a0 must be connected to v dd or v ss . the remaining bits of the slave address are fixed internally. 7.7 i 2 c-bus data con?guration the PCD4440T is always a slave receiver in the i 2 c-bus configuration (the r/ w bit = 0). the slave address consists of 7 bits, where the least significant is set by the input on a0. the more significant bits are fixed internally, as shown in fig.5. for definition of d0-d4, see table 1. 7.8 signal input (in), signal output (out) signal input for the scrambler/descrambler is coupled into a sallen and key anti-aliasing filter configuration. a dc bias voltage of 1 2 v dd is built-in. the analog signal output is buffered to achieve a relatively low output impedance of roughly 1 k w which is sufficient to drive the earpiece amplifier or similar applications. handbook, full pagewidth mgg732 s 110111a00a0000d3d2d1d0a p slave address data r/w msb acknowledge acknowledge internal strobe fig.5 i 2 c-bus data format.
1996 dec 20 9 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 8i 2 c bus interface the i 2 c-bus is for two-way communication between different ics or modules. it uses only two lines, a serial data line (sda) and a serial clock line (scl), both of which are bi-directional. both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer (see fig.6) one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 8.2 start and stop conditions (see fig.7) both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). fig.6 bit transfer. mbc621 data line stable; data valid change of data allowed sda scl fig.7 start and stop conditions. mbc622 sda scl p stop condition sda scl s start condition
1996 dec 20 10 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 8.3 system con?guration (see fig.8) a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls message transfer is the master and the devices that are controlled by the master are the slaves. 8.4 acknowledge (see fig.9) the number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master generates an extra acknowledge after the reception of each byte. also a master must generate an acknowledge after reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge-related clock pulse. set-up and hold times must be taken into account to ensure that the sda line is stable low during the whole high period of the acknowledge-related clock pulse. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate the stop condition. fig.8 system configuration. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl fig.9 acknowledgment on the i 2 c-bus. mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
1996 dec 20 11 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 8.5 timing speci?cations the PCD4440T accepts data input from a microcontroller and operates as a slave receiver via the i 2 c-bus. it supports the standard mode of the i 2 c-bus, but not the fast mode detailed in the i 2 c-bus and how to use it document order no. 9398 393 40011. the timing requirement are as follows: masters generate a bus clock with a maximum frequency of 100 khz. detailed timing is shown in fig. 10, where the two signal levels are low = v il and high = v ih , see chapter 12. the time symbols are explained in table 2. figure 11 shows a complete data transfer. fig.10 standard mode timing. handbook, full pagewidth mbc764 t buf t f t high t su;dat t su;sto t hd;dat t su;sta t r t low t hd;sta sda scl sda fig.11 complete data transfer in standard mode. handbook, full pagewidth mbc765 9 8 1 - 7 9 8 1 - 7 9 8 1 - 7 stop ack address r/w start condition ack data start condition ack address r/w scl sda clock low minimum = 4.7 m s; clock high minimum = 4 m s. the dashed line is the acknowledgment of the receiver. mark-to-space ratio = 1 : 1 (low-to-high). maximum number of bytes is unrestricted. premature termination of transfer is allowed by generation of stop condition. acknowledge clock bit must be provided by master.
1996 dec 20 12 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T table 2 explanation of time symbols used in fig.10 symbol parameter description min. max. units f scl scl clock frequency 0 100 khz t sw tolerable pulse spike width - 100 ns t buf bus free time the time that the bus is free (sda is high) before a new transmission is initiated by sda going low. 4.7 -m s t su;sta set-up time repeated start only valid for repeated start code. 4.7 -m s t hd;sta hold time start condition the time between sda going low and the ?rst valid negative-going transition of scl. 4.0 -m s t low scl low time the low period of the scl clock. 4.7 -m s t high scl high time the high period of the scl clock. 4.0 -m s t r rise time sda and scl - 1.0 m s t f fall time sda and scl - 0.3 m s t su;dat data set-up time 250 - ns t hd;dat data hold time 0 - ns t su;sto set-up time stop condition 4.0 -m s
1996 dec 20 13 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 9 applications fig.12 ct0 handset with direct (manchester code) data system. handbook, full pagewidth mgg733 rf section microcontroller pcd33xxa a/d converter antenna descrambler PCD4440T expandor 1/2 ne577 scrambler PCD4440T compressor 1/2 ne577 detector lcd driver lcd display data in data out mod tx rx i 2 c-bus rssi power down rx power down tx v ref keypad 123 456 789 * 0#
1996 dec 20 14 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, it is good practice to take normal precautions appropriate to handling mos devices (see handbook ic03, section general, handling mos devices ). fig.13 ct0 base unit with direct (manchester code) data system. handbook, full pagewidth mgg734 rf section microcontroller pcd33xxa a/d converter antenna descrambler PCD4440T line interface tea106x expandor 1/2 ne577 scrambler PCD4440T compressor 1/2 ne577 detector charging circuit dtmf data in data out mod tx rx i 2 c-bus rssi power down rx power down tx telephone line v ref
1996 dec 20 15 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 11 limiting values in accordance with the absolute maximum rating system (iec 134). 12 characteristics v dd = 5.0 v; v ss =0v; t amb =25 c; all voltages with respect to v ss ; f xtal = 3.579 mhz unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage - 0.3 +7.0 v v i all input voltages - 0.8 v dd + 0.8 v i i dc input current - 10 +10 ma i o dc output current - 20 +20 ma p tot total power dissipation - 300 mw p o power dissipation per output - 50 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature - 25 +70 c symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 2.8 - 6.0 v i dd supply current mute mode v dd =3v - 2.2 - ma operating mode v dd =3v - 13 - ma inputs/outputs: ao, sda, scl v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v c i input capacitance -- 7pf i ol sda output current low v ol = 0.4 v 3.0 -- ma signal input: in v dc dc voltage level - 0.5v dd - v v i(p-p) allowed amplitude - 1.25 v dd - 1v | z i | input impedance frequency = 1 khz - 120 - k w signal output: out v dc dc voltage level - 0.5v dd - v | z o | output impedance frequency = 1 khz -- 1k w ufs unwanted frequency suppression v i(p-p) = 1.25 v; f s = 767 or 2461 hz; f in = 1 khz; v dd =3vor5v 35 40 - db v o /v i transfer loss transparent mode - 3.5 - db operating mode - 0 - db oscillator frequency input: osci v dc dc voltage level - 0.5v dd - v v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v
1996 dec 20 16 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 13 package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) z (1) eh e ll p qy w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 7.65 7.45 7.6 7.4 1.27 10.65 10.00 1.1 1.0 2.0 1.8 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.45 sot176-1 91-08-13 95-02-25 x 4 8 q a a 1 a 2 w m b p d h e l p q detail x e z e c l v m a 5 1 (a ) 3 a y 0.25 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.30 0.29 0.30 0.29 0.050 1.45 0.057 0.25 0.01 0.42 0.39 0.043 0.039 0.079 0.071 0.01 0.004 0.043 0.018 0.01 0 5 10 mm scale pin 1 index so8: plastic small outline package; 8 leads; body width 7.5 mm sot176-1
1996 dec 20 17 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 14 soldering 14.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 14.2 re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 14.3 wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 dec 20 18 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 dec 20 19 philips semiconductors product speci?cation analog voice scrambler/descrambler PCD4440T notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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